Introduction
Intheentiredesignprocess,thestandarddelayformathasimportantapplications,suchasstatictiminganalysis.
InstituteofElectricalandElectronicsEngineers
InstituteofElectricalandElectronicsEngineers(English:InstituteofElectricalandElectronicsEngineers,abbreviatedasIEEE,pronouncedinEnglishas"itriplee"[aitrɪpli:])isanestablishmentTheInternationalAssociationofElectronicTechnologyandElectronicEngineers,establishedonJanuary1,1963,isalsooneofthelargestprofessionaltechnicalorganizationsintheworld,with360,000membersfrom175countries.
InadditiontotheheadquartersinNewYorkCity,USA,italsohaschaptersinmorethan150countriesaroundtheworld,andthereare35professionalsocietiesand2federations.Itpublishesavarietyofmagazines,journals,andbookseveryyear,andalsoholdsatleast300professionalconferences.
Currently,thestandardsdefinedbyIEEEintheindustryhaveagreatinfluence.
Integratedcircuitdesign
Integratedcircuitdesign(English:Integratedcircuitdesign,ICdesign),accordingtothecurrentintegratedcircuitdesignTheintegrationscalecanalsobereferredtoasVLSIdesign(VLSIdesign),whichreferstothedesignprocesstargetingintegratedcircuitsandVLSI.
Integratedcircuitdesignusuallytakes"module"asthedesignunit.Forexample,foramulti-bitfulladder,thesecondarymoduleisaone-bitadder,andtheadderiscomposedofthenextlevelofANDandNOTmodules.TheNANDandNOTgatescanfinallybedecomposedintolowerabstractions.GradeCMOSdevice.
Fromanabstractlevel,digitalintegratedcircuitdesigncanbetop-down,thatis,thefunctionalmodulesofthehighestlogiclevelofthesystemaredefinedfirst,andthesub-modulesaredefinedaccordingtotherequirementsofthetop-levelmodules,andthenlayerbylayerContinuetodecompose;thedesigncanalsobebottom-up,thatis,themostspecificmodulesaredesignedfirst,andthentheselowest-levelmodulesareusedasbuildingblockstorealizetheupper-levelmodules,andfinallyreachthehighestlevel.Inmanydesigns,top-downandbottom-updesignmethodologiesaremixed.Thesystem-leveldesignersplantheoverallarchitectureanddividethesub-modules,whilethebottom-levelcircuitdesignersdesignupwardslayerbylayer.,Optimizeindividualmodules.Finally,designersfromthetwodirectionsmeetatacertainlevelofabstractioninthemiddletocompletetheentiredesign.
StaticTimingAnalysis
StaticTimingAnalysis(English:StaticTimingAnalysis,STA),orStaticTimingverificationisaworkprocessforcalculatingandpredictingthetimingofdigitalcircuitsinelectronicengineering.Theprocessdoesnotneedtobesimulatedbyinputexcitation.
Traditionally,peopleoftenregardtheoperatingclockfrequencyasoneofthecharacteristicsofhigh-performanceintegratedcircuits.Inordertotesttheabilityofacircuittooperateataspecifiedrate,peopleneedtomeasurethedelayofthecircuitindifferentstagesofoperationduringthedesignprocess.Inaddition,indifferentdesignstages(suchaslogicsynthesis,placement,routing,andsomesubsequentstages),delaycalculationsneedtobeperformedinsidethetimeoptimizationprogram.AlthoughthistypeoftimemeasurementcanbeperformedthroughrigorousSPICEcircuitsimulation,thismethodconsumesalotoftimeinpractice.Statictiminganalysisplaysanimportantroleinthefastandaccuratemeasurementofcircuittiming.Statictiminganalysiscancompletetasksmorequicklybecauseitusesasimplifiedmodel,andittakesintoaccountthelogicalinteractionsbetweensignalstoalimitedextent.Statictiminganalysishasbecomethemaintechnicalmethodinrelateddesignfieldsinrecentdecades.
Oneoftheearliestdescriptionsofstatictiminganalysisisbasedonthe1966planevaluationtechnique.Someofitsmoremodernversionsandalgorithmsappearedintheearly1980s.