Hardware verification language


Hardware verification language typically has a feature similar to the advanced language like C ++ or Java, while providing bit operational functions like hardware description languages. Many hardware verification languages ​​can generate a constrained random incentive, and provide a functional coverage structure to assist designers to perform complex hardware verification.

SystemverLOG, OpenVERA, and Systemc are the most commonly used hardware verification languages. Among them, SystemverIlog is more combined with hardware description language to hardware verification languages ​​to a single standard.

Hardware Description Language

In electronics, hardware description language (English: Hardware Description Language, HDL ) is used To describe the language of the electronic circuit (especially digital circuit), behavior, the digital circuit system can be described in the register transfer stage, behavioral level, logical gate level, etc. With the development of automation logic, hardware description languages ​​can be identified by these tools, and automatically convert to logical gate-class network tables such that the hardware description language can be used to perform circuit system design, and verify the circuit through logical simulation Function. Once the design is complete, you can use a logical integrated tool to generate a low-abstract level (door-class) network table (ie wiring table).

Hardware verification language

Hardware Description Language may be similar to traditional software programming languages, but the biggest difference is that the former can describe the timing characteristics of the hardware circuit. Hardware description languages ​​are an important part of the electronic design automation system. Small to simple triggers, large to complex large scale integrated circuits, such as microprocessors, can be described using hardware description languages. Common hardware description languages ​​include Verilog, VHDL, etc.


The design and verification process of the integrated circuit (especially the large scale integrated circuit), SystemverIlog is developed by Verilog Hardware description, hardware verification uniform language, the former part is basically the extension of 2005 version of Verilog, and a part of the functional verification characteristics is an object-oriented programming language. Object-oriented characteristics are well compensated for the defects of traditional Verilog in the field of chip verification, improved code reusability, while allowing verification engineers to have higher abstract levels than register levels, transactions, as monitored objects, These have greatly improved the efficiency of the verification platform.

Systemverilog has been adopted as the Electrical Electronics Engineer Society 1800-2009 standard and has obtained the support of mainstream electronic design automation tools. Although no simulation system can fully support all language structures introduced in the SYSTEMVERILANUAL, LRM, it is difficult to improve the interoperability of the test platform, but promote research and development of cross-platform compatibility. It is already in progress. Several verification methods have appeared successively, standardizing the test platform modules in the form of a predefined class, and now the latest systemverilog-based authentication methods are commonly verified. This methodology mainly includes an open source class library and supports a reusable test platform to develop a preset format for verifying an IP core. Many third-party providers have begun to launch a virtual IP core based on Systemverilog.


OpenVERA is a hardware verification language, which is developed and operated by Jindi Technology. This language is mainly used to create a test platform for hardware systems. OpenVERA is a basic part of the IEEE1800 standard SYSTEMVERILOG, many people engaged in semiconductor integrated circuit design, system-level design, IP nuclear design, and electronic design automation benefit from this.


systemc is a computer language based on the system design of the C ++ language, a set of libraries and macros prepared with C ++. It is the product that gradually develops to improve electronic system design efficiency. IEEE approved the IEEE1666-2005 standard in December 2005.

typically, the system consists of software part and hardware part, and a part of the system is implemented by software, while another part of the function is implemented by hardware. Early system is relatively simple, system engineers will be prepared to design, design, simulate, implement and improve software engineers and hardware engineers, and finally combine software parts and hardware components, respectively. Software engineers use programming languages ​​such as C and C ++, because these languages ​​are specialized to describe the serial execution procedures, and hardware engineers use hardware description languages ​​such as VHDL and Verilog, because these languages ​​are described in parallel. Hardware, used to simulate hardware parts. However, with the continuous development of the electronic system, the system structure is increasing, and there are more and more system components, which requires system engineers to have a good understanding and master of the entire system when they are in secondary software and hardware. To better divide software and hardware, reduce the loss and risks of unnecessary mistakes in the design. SYSTEMC is also born with this because it meets the needs of software and hardware synergies.

Systemc system and "C / C ++ Language" in English C To indicate that it is a system design language based on C / C ++ language.

Many scientific research teams and computer-aided design software have contributed to the development of SYSTEMC. In 1999, the Open SYSTEMC ITIATIVE (OSCI) "has been established in 1999.

November 10, 2011, IEEE passed the new SYSTEMC 2011 standard: IEEE1666-2011.

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