A clock interruption detecting circuit comprising: an input clock frequency to a different scale value and output a plurality of frequency divider circuits of a clock; input clock and a plurality of frequency-divided clock "and" "and" circuit operation; an inverter having an inverted frequency-divided clock dividing the maximum value; the remaining input clock frequency-divided clock and the inverter output "and and "operation" "circuitry; is provided to the respective first and second switches, having a" control terminal "of the output circuit, the control ON / oFF of the first and second capacitors discharge path; a first and second wave form the buffer circuit is supplied to the terminal voltage of the first and second capacitors; obtained according to the length of the delay circuit manipulation inverter output a predetermined time delay selection control signal an output buffer circuit formed of first and second waveforms selection circuit. Which causes the input clock by a single system clock interrupts can be detected more easily integrated, and the clock interruption time can be accurately detected.
and the initial value of the timer interrupt cycle clock interrupt without too frequently, and generally 20mS (50Hz) can be. The time base signal needs to hundredths of a second, preferably 10mS (100Hz). Here take 20mS, T0 timer operating in 16-bit timer mode (mode 1). T0 works as follows: every machine cycle is automatically incremented when the count full 0FFFFh, to overflow, it will generate an interrupt by setting the corresponding flag bit hardware for software polling. After the machine cycle N + 1 than the start of the interrupt. So, we just T0 pre-stored in a smaller number than the full value 0FFFFh N, and then start the timer, it will generate an interrupt after N machine cycles. This value is the so-called "initial value." The calculation of the initial value we need: the clock is 6MHz, 12 clock periods of a machine cycle, 20mS there are 10,000 machine cycles. (10000) = 10 (2710) 16, the 0FFFFh-2710h + 1 = 0D8F0h. Since the response to the interrupt, and reload the initial value field protection required 7-8 machine cycles, this value plus 7, i.e., T0 is the initial value should be loaded 0D8F7h. After each interrupt entry, and the value of the PSW A first pushed onto the stack, i.e. the 0D8F7h then loaded T0.
a setting unit, plus 1 each interrupt internal RAM we can take a unit named INCPI (Increase Per Interrupt), in the interrupt, the initial value T0 Bahrain, with the instruction INC INCPI it is a plus. From this unit, the main program or whether the program interrupt, a signal can be obtained from any integer multiple of 20mS between 256 ~ 1. For example: There was a significant fed to the digital program needs to be performed once every 0.5 seconds in order to refresh the display, it may be provided a unit (referred to as a waiting cell) W_DISP, with / MOV A, INCPI / ADD A, # 25 / MOV W_DISP , a / statements allowed larger than the current value of INCPI 25, and then check whether each interrupt to INCPI values are equal. If equal, indicating passed 25 interrupt cycles, will send significant program execution, and let W_DISP plus 25, wait for the next 0.5 seconds. We can wait a plurality of units, in order to extract a plurality of different time base. Let interrupt program each time you interrupt and then click Query whether each unit and wait INCPI equal, if equal, the corresponding process is executed, and reset the value of the waiting unit, otherwise skip. Eg: 0.5 seconds or flashing display refresh signal, square wave generating real-time clock, or a constant frequency output signal with one second, at intervals query input devices.
read in the interrupt button Usually, we read the keyboard in the main program, the steps of: scanning the keyboard, if any key is pressed, the delay tens of milliseconds to shake, indeed Press this button again to confirm and try again after the above step process corresponding to the key operation, is completed. But there are two shortcomings: 1 can not latch input keys corresponding processing work that may leak key. 2. Delay CPU can not do other things to shake when the efficiency is not high. If the read key into the clock interrupt, you can avoid these shortcomings. Method: If the two are adjacent to the interrupt to read the same key is pressed, then the key is valid (up to the debounce purposes), and is latched into the FIFO (queue) keyboard buffer , and other main program to deal with. Thus, while the main program keys, still in response to keyboard input. Typically the depth buffer may be set to 8, if the number of keys than the latch 8, a new key is ignored, and the new alarm the user key will be invalid. If the keyboard buffer queue stagnation time much longer than the main key processing time required for the maximum, indicating that the main program runaway or erroneous, the system may be interrupted with a reset instruction, a purpose of the watchdog functions.
in the main routine since the normally open delay clock interrupt, the main program when the necessary time is shorter, the higher the accuracy of the delay, the clock interrupt should be temporarily closed. When the program longer, high accuracy is not required delay, it can be modeled under the required writing, to avoid the nested loop delay.
Example: P1.1 in 1 second high-level pulse output
MOV A, INCPI
CJNE A , INCPI $; wait for the next interrupt processing is completed
SETB P1.1; P1.1 provided is H, pulse starts
ADD A, # 50; 50 th 20mS 1 sec < / p>
CJNE a, INCPI, $; et interrupt INCPI plus a 50
CLR P1.1; P1.1 set as L, the end of pulse
below for example with MCS-51:
MCS-51 interrupt response process:
1, in response to the interrupt condition: talked about here, we still feel the magic interrupt for the computer to respond, we people can respond to external events, because we have multiple "sensors" - eyes, ears can accept different information, how the computer do it? Put bluntly, is not surprising, when MCS51 work in each machine cycle will go to check what each interrupt flag to see if they are "1", if it is 1, it means that there is an interrupt request, so-called interrupt, actually query, but each cycle check it. That adults want to change, you're in the equivalent of reading, looked up to see every second, to check what is not someone rang the doorbell, if there is a telephone. . . . Stupid, is not it? The computer may have been like this, it did not clever people.
understand the above-described interrupt process, the interrupt condition is not the obscure. When one of the following three cases, CPU blocks the response to interruptions:
CPU is processing the same level or a higher level of the interrupt request. The current machine cycle is not the last cycle currently executing instruction. We know that there are single-chip single-cycle, two-cycle, the three-cycle instruction, the currently executing instruction is a single byte does not matter, if it is double-byte or four bytes, would have to wait the entire instruction is executed over, in order to respond to the interrupt ( because the query is interrupted at each machine cycle are likely to be found).
is the current instruction being executed to return the batch command (the RETI) or the IP access, the instruction register IE, then the CPU executing at least one instruction should only be interrupted. These are related to, if you are accessing IP, IE might open and interrupt disable interrupts interrupt or change the priority of the interrupt return instruction is illustrated in this interruption has not been processed, so have to wait for the end of processing this directive and then execute one instruction before they can respond to interrupts.
2, the interrupt process
When the CPU interrupt, the first of the next instruction of the current instruction (that is, upon return from interrupt instruction to be executed) into the address of the stack, and then in accordance with interrupt flag, the corresponding interrupt entry address into the PC, a program pointer PC, the CPU will fetch the PC according to the value, the value of what the PC, where it will pick up the instruction, so the program will branch to the interrupt the entrance continues. This work is done by the hardware, we do not have to consider. There is also a problem, if you've noticed, each interrupt vector addresses separated by only eight units, such as 0003-000B, how to complete the interrupt routine in such a small space it? Very simple, you arrange a LJMP instruction in place, you can not interrupt the program to jump to any place yet?
a complete main program should look like this:
LJMP INT0; transfected external interrupt 0
RETI; 0 no timer interrupt, the RETI here put one, in case "do not care" interrupt there will not be much effect. After
interrupt process is completed, be sure to execute a RETI instruction after this instruction is executed, CPU will stack holds the address out, back to PC, then the program will be interrupted from the main program Department continued to implement down. Note: CPU protection work is very limited, only the protection of an address, and all other things are not protected, so if you like to use the A, PSW in the main program, etc., but also with the interrupt routine them, but also to ensure the return to the main program after there is data or not executed before the interrupt data, you have protected yourself.
From seen to be flexible application of the clock interrupt, the interrupt and rational allocation of tasks to the main program, and both want to clear division of labor, simple interface. This is one of the skills we also need a lot of trial and error and experience in practice. Also note: should try to shorten the interrupt handler execution time, not longer than 20mS.