Návrh zahrnuje
Theflowofintegratedcircuitdesigngenerallyfirstneedstobedividedintosoftwareandhardware,andthedesignisbasicallydividedintotwoparts:chiphardwaredesignandsoftwareco-design.Chiphardwaredesignincludes:
1.Fáze funkčního návrhu.
Designer’sproductapplicationoccasions,setsomespecificationssuchasfunction,operatingspeed,interfacespecifications,environment
environmenttemperatureandpowerconsumption,etc.,asafuturecircuitdesigninaccordancewith.Itcanfurtherplanhowsoftwaremodulesandhardwaremodulesshouldbedivided,whichfunctionsshouldbeintegratedintheSOC,andwhichfunctionscanbedesigned
vypočítané na desce plošných spojů.
2.Popis návrhu a ověření na úrovni chování
Afterthefunctiondesigniscompleted,theSOCcanbedividedintoseveralfunctionalmodulesaccordingtothefunction,andtheIPcoresthatwillbeusedtoimplementthesefunctionsaredetermined.
ThisstageindirectlyaffectstheinternalstructureoftheSOCandtheinteractivesignalsbetweenvariousmodules,aswellasthereliabilityoffutureproducts.
Afterdecidingthemodule,youcanusehardwaredescriptionlanguagesuchasVHDLorVerilogtorealizethedesignofeachmodule.
Then,usethecircuitsimulatorofVHDLorVerilogtoverifythedesign(function
simulace, nebobehaviorální simulace).
Notethatthiskindoffunctionalsimulationdoesnotconsidertheactualdelayofthecircuit,norcanitobtainaccurateresults.
3. Logická syntéza
Afterconfirmingthatthedesigndescriptioniscorrect,youcanusethelogicsynthesistool(synthesizer)forsynthesis.
Inthesynthesisprocess,youneedtoselecttheappropriatelogiccelllibraryasareferencewhensynthesizinglogic
obvody.
Thewritingstyleofthehardwarelanguagedesigndescriptionfileisanimportantfactorthatdeterminestheexecutionefficiencyofthesynthesistool.
Infact,theHDLsyntaxsupportedbysynthesistoolsislimited,andsometooabstractsyntax
isonlysuitableasasimulationmodelforsystemevaluationandcannotbeacceptedbysynthesistools.
Logicsynthesis získá síťový seznam na úrovni brány.
4.Gate-LevelNetlistVerification
Gate-LevelNetlistVerificationisaregistertransfer-levelverification.Themaintaskistoconfirmwhethertheintegratedcircuitmeetsthefunctionalrequirements.Thistaskisgenerallycompletedwithagate-levelverificationtool.
Notethatthedelayofthegatecircuitneedstobeconsideredinthesimulationatthisstage.
5.Layoutandrouting
Layoutreferstorationallyarrangingthedesignedfunctionalmodulesonthechipandplanningtheirlocations.Wiringreferstothewiringthatcompletestheinterconnectionbetweenmodules.Notethattheconnectionbetweeneachmoduleisusuallyrelativelylong,sotheresultingdelaywillseriouslyaffecttheperformanceoftheSOC,especiallyinthe0.25micronprocessandabove,thisphenomenonismoresignificant.Atpresent,thisindustryisstillavacancyinChina,andtherearestillrelativelyfewuniversitiesofferingintegratedcircuitdesignandintegratedsystems.Amongthem,schoolswithbetterteachersincludeShanghaiJiaotongUniversity,HarbinInstituteofTechnology,HarbinUniversityofScienceandTechnology,SoutheastUniversity,andXi’anElectronicTechnology.University,UniversityofElectronicScienceandTechnologyofChina,FudanUniversity,EastChinaNormalUniversity,etc.Thisfieldhasgraduallybecomesaturated,andthereisagrowingtrendtofollowthepathofthesoftwareindustryinthosedays.
Proces návrhu
1. Návrh obvodů
Completethecircuitdesignaccordingtothecircuitfunction.
2.Předsimulace
Simulationofcircuitfunctions,includingsimulationofpowerconsumption,current,voltage,temperature,voltageswing,inputandoutputcharacteristicsandotherparameters.
3. Návrh rozvržení (Rozvržení)
Drawthelayoutbasedonthedesignedcircuit.Cadencesoftwareisgenerallyused.
4.Po simulaci
Simulatethedrawnlayoutandcompareitwiththeprevioussimulation.Ifitfailstomeettherequirements,thelayoutneedstobemodifiedorredesigned.
5.Následné zpracování
TheGDSIIfileisgeneratedfromthelayoutfileandsubmittedtoFoundryfortape-out.