The storage bus is composed of many parallel data transmission lines, which are subdivided into three groups: data bus (used to transfer data); address bus (used to transfer main Memory address); control bus (used for the transmission of various internal control commands).
The information exchange between the CPU and the main memory is carried out through the data bus and the address bus. When the CPU needs information, it needs to give address information. For the main memory to read the information, the address must first be sent to the address bus, and a "read" signal is sent out through the control bus. These signals are transferred to the main memory, and several consecutive memory cells with specified addresses are read out and sent to the data bus. Then, the CPU can get the data from the data bus. The write action is similar. It can be seen from the read and write operation process that when the CPU sends out the address, the read data can be obtained from the data bus after a certain period of time, which is determined by the working speed of the main memory and the working speed of the data bus.
The width of the data bus is generally determined by the data width of the CPU chip. The CPU generally uses a 32-bit or 64-bit data bus. The width of the data bus determines the amount of data transferred at one time through it.
In medium and small computers, because the CPU must constantly fetch instructions, fetch operands, and send results during the working period of the CPU, the information flow between the CPU and the main memory MM The flux is particularly large, a multi-bus structure is to add a set of buses between the two busiest components. This group of buses is usually called the memory bus, which is a local bus.